With semi-conductor components, in particular memory components such as DRAMs (DRAM=Dynamic Random Access Memory and/or dynamic read-write memories—e.g. based on CMOS technology—so-called clock pulses are used for the chronological coordination of the processing and/or relaying of data.
With conventional semi-conductor components a single clock pulse (i.e. a so-called “single ended” clock pulse)—present on a single line—is used).
The data can then for instance be relayed during each ascending pulse flank of the single clock pulse (or alternatively for instance during each descending single clock pulse flank).
Furthermore, in current technology so-called DDR components, in particular DDR-DRAMs (DDR-DRAM=Double Data Rate DRAM and/or DRAM with a double data rate), are already well known.
With DDR components—instead of a single clock pulse (“single ended” clock pulse) present on a single line—two differentiated, reciprocally inverse clock pulses present on two separate lines are used.
Every time, for instance when the first of the two clock pulses changes its state from “high logic” (e.g. a high voltage level) to a state of “low logic” (e.g. a low voltage level), the second clock pulse—essentially simultaneously—changes its state from “low logic” to “high logic” (e.g. from a low to a high voltage level).
Conversely, whenever the first clock pulse changes its state from “low logic” (e.g. a low voltage level) to a state of “high logic” (e.g. a high voltage level), the second clock pulse (again essentially simultaneously) changes its state from “high logic” to “low logic” (e.g. from a high to a low voltage level).
In DDR components, data is usually relayed during the ascending flank of the first clock pulse, as well as during the ascending flank of the second clock pulse (and/or also during the descending flank of the first clock pulse, as well as during the descending flank of the second clock pulse).
Therefore, data in a DDR component is relayed more frequently and/or faster (in particular twice as frequently, and/or twice as fast) as in corresponding conventional components with single—and/or “single ended”—clock pulses—i.e. the data rate is higher, in particular twice as high as in corresponding conventional components.
The—internal—clock pulse (“DQS” and/or “data strobe” signal and/or—where differentiated, reciprocally inverse clock pulses are used—the internal clock pulse DQS and the clock pulse BDQS, reciprocally inverse to the clock pulse DQS used in the component for the chronological coordination of the processing and/or relaying of data, must be applied synchronously with an external clock pulse (“CLK” and/or “clock” signal) and/or synchronously with a differentiated clock pulse CLK, BCLK, externally entered into the component).
The external clock pulses CLK, BCLK are generated by an appropriate external clock pulse generator connected to the component.
In order to synchronize the internally generated clock pulse DQS and/or the internally generated clock pulses DQS, BDQS with the external clock pulses CLK, BCLK, a clock pulse synchronization apparatus, e.g. a DLL circuit (DLL=Delay Locked Loop) is used. Such a circuit is known from EP 964 517 for instance.
A clock pulse synchronization apparatus may for instance contain a first delay facility (“delay chain”), into which the external clock pulses CLK, BCLK are entered, and which—depending on a control signal emitted by a phase comparator—applies a variable delay period tvar—adjustable by the control signal—to the entered clock pulses CLK, BCLK.
The delay period tvar is for instance variable between a certain minimum delay period tvar,min (which may be equal to or approximately equal to zero), and a particular maximum delay period tvar,max.
The signal(s) emitted by the first delay apparatus can then be used—internally—in the component for the chronological co-ordination of the processing and/or relaying of data (i.e. as the—internal—clock pulse(s) DQS and/or BDQS).
The signal DQS emitted by the first delay apparatus is relayed to a second delay apparatus (“clock tree delay mimic”), which applies a—fixed—delay period tconst, to the entered signal DQS corresponding approximately to the sum total of the signal delays caused by the receiver (“receiver delay”), and/or each data path (“data path delay”) and/or the off-chip driver (“OCD delay”).
The signal (FB signal and/or “feedback signal” emitted by the second delay apparatus) is relayed to the above phase comparator apparatus, where the phase status of the FB signal is compared with that of the CLK signal (similarly entered into the phase comparator apparatus). Depending on whether the phase of the FB signal precedes that of the CLK signal or trails behind it, an increasing signal (INC signal) or decreasing signal (DEC signal) is emitted by the phase comparator apparatus as control signal for the above first delay apparatus, which causes the delay tvar of the CLK signal, imposed by the first signal delay apparatus—in case of an INC signal—to be increased, and/or—in case of a DEC signal—to be reduced so that the CLK and the FB signals are synchronized, i.e. so that the clock pulse synchronization apparatuses are “locked”.
The frequency of the clock pulses (CLK, BCLK) entered into the component and/or the DLL circuit (e.g. as laid down in the corresponding specification of the semi-conductor component) should if possible not be changed—particularly when the DLL circuit is in an “unlocked” state.
In particular, when the frequency of the clock pulses (CLK, BCLK) entered into the component and/or the DLL circuit is—nevertheless—changed (e.g., to conserve energy, when booting up the system, etc.) the delay period tvar may be changed to such an extent during the synchronization process caused by the first delay apparatus (“delay chain”), that the delay period can approach its upper or lower limits (e.g. the lower limit—e.g. the zero delay tvar,min=0—, or e.g. the upper limit (tvar,max)—amounting to the maximum number of delay units).